Data transmission is an important part of many integrated circuits and systems having integrated circuits. Data is typically communicated with an integrated circuit by way on an input/output (I/O) port. Data may be communicated in a system in different formats and according to a variety data communication protocols. However, a receiver of an integrated circuit can consume significant power and can have a significant effect on the operation of an integrated circuit having the receiver. Accordingly, circuit designers are always looking for ways to improve the operation and performance of a receiver in an integrated circuit device.
It is becoming more difficult to implement General Purpose Input/Output (GPIO) receiver designs that meet the design constraints of conventional high speed, low power, low signal swing applications, such as double data rate (DDR4), mobile industry processor interface (MIPI), sub-low voltage differential signaling (sub-LVDS), etc., which have low input signal swing. Due to mismatches in the circuit layout and random process variations of integrated circuit devices, the input offset voltage of a typical receiver can be at such a high level that it reduces the net input swing of the receiver to an unacceptably low level. It is hard to meet 3.2 Gbps data rate of a DDR4 interface with 20 mV input signal swing using existing receiver designs due to their limited input sensitivity, bandwidth, and high pad capacitance. Further, receivers having reduced power consumption and improved performance are beneficial when implemented in integrated circuit devices.